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This is a hierarchical entity that can have other modules or processes contained in it. SystemC has a notion of a container class called a module. SystemC version 2 added abstract ports, dynamic processes, and timed event notifications. From version 2 onward, the focus of SystemC has moved to communication abstraction, transaction-level modeling, and virtual-platform modeling. SystemC version 1 included common hardware-description language features such as structural hierarchy and connectivity, clock-cycle accuracy, delta cycles, four-valued logic (0, 1, X, Z), and bus-resolution functions. The performance of the OSCI open-source implementation is typically less optimal than commercial VHDL/Verilog simulators when used for register transfer level simulation. Source code can be compiled with the SystemC library (which includes a simulation kernel) to give an executable. Although strictly a C++ class library, SystemC is sometimes viewed as being a language in its own right. On the other hand, it offers a greater range of expression, similar to object-oriented design partitioning and template classes. SystemC has semantic similarities to VHDL and Verilog, but may be said to have a syntactical overhead compared to these when used as a hardware description language. Although it was the intent of OSCI that commercial vendors and academia could create original software compliant to IEEE 1666, in practice most SystemC implementations have been at least partly based on the OSCI proof-of-concept simulator. OSCI also provide an open-source proof-of-concept simulator (sometimes incorrectly referred to as the reference simulator), which can be downloaded from the OSCI website. The LRM provides the definitive statement of the semantics of SystemC.

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SystemC is defined and promoted by the Open SystemC Initiative (OSCI - now Accellera), and has been approved by the IEEE Standards Association as IEEE 1666-2011 - the SystemC Language Reference Manual (LRM).

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